PnR Messages

Report Title PnR Report
Design File /home/quang1806/Desktop/ACG525_TEST/ch26_hdmi_color (2)/impl/gwsynthesis/gao_hdmi_color.vg
Physical Constraints File /home/quang1806/Desktop/ACG525_TEST/ch26_hdmi_color (2)/src/gao_hdmi_color.cst
Timing Constraints File /home/quang1806/Desktop/ACG525_TEST/ch26_hdmi_color (2)/src/time.sdc
Tool Version V1.9.11
Part Number GW1NSR-LV4CQN48PC6/I5
Device GW1NSR-4C
Created Time Thu Jun 26 10:23:52 2025
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

PnR Details

Place & Route Process Running placement: Placement Phase 0: CPU time = 0h 0m 0.048s, Elapsed time = 0h 0m 0.054s Placement Phase 1: CPU time = 0h 0m 0.198s, Elapsed time = 0h 0m 0.198s Placement Phase 2: CPU time = 0h 0m 0.016s, Elapsed time = 0h 0m 0.016s Placement Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s Total Placement: CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s Running routing: Routing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.011s Routing Phase 1: CPU time = 0h 0m 0.206s, Elapsed time = 0h 0m 0.21s Routing Phase 2: CPU time = 0h 0m 0.33s, Elapsed time = 0h 0m 0.336s Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s Total Routing: CPU time = 0h 0m 0.536s, Elapsed time = 0h 0m 0.557s Generate output files: CPU time = 0h 0m 0.439s, Elapsed time = 0h 0m 0.449s
Total Time and Memory Usage CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 246MB

Resource

Resource Usage Summary:

Resource Usage Utilization
Logic 201/4608 5%
    --LUT,ALU,ROM16 201(171 LUT, 30 ALU, 0 ROM16) -
    --SSRAM(RAM16) 0 -
Register 107/3573 3%
    --Logic Register as Latch 0/3456 0%
    --Logic Register as FF 107/3456 4%
    --I/O Register as Latch 0/117 0%
    --I/O Register as FF 0/117 0%
CLS 130/2304 6%
I/O Port 11/39 29%
I/O Buf 11 -
    --Input Buf 2 -
    --Output Buf 9 -
    --Inout Buf 0 -
IOLOGIC 8 ODDR
 16%

I/O Bank Usage Summary:

I/O Bank UsageUtilization
bank 0 1/912%
bank 1 1/1010%
bank 2 8/989%
bank 3 5/1146%

Clock Resource Usage Summary:

Clock Resource Usage Utilization
PRIMARY 1/8 13%
LW 0/8 0%
GCLK_PIN 3/5 60%
CLKDIV 1/6 17%
PLLVR 1/2 50%

Global Clock Signals:

Signal Global Clock Location
clk_vga PRIMARY LEFT RIGHT
clk_vgax5 HCLK RIGHT[1]

Pinout by Port Name:

Port Name Diff Pair Loc./Bank Constraint Dir. Site CFG IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor BankVccio
clk - 45/1 Y in IOT13[A] LPLL_T_in LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
rst_n - 14/3 Y in IOB4[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
led - 21/3 N out IOB16[B] GCLKC_5 LVCMOS18 8 NONE NA NA OFF NA NA NA 1.8
tmds_clk_p - 28/2 Y out IOR17[A] - LVCMOS33D 8 NONE NA NA NA NA OFF NA 3.3
tmds_clk_n - 8/0 N out IOT4[B] JTAGSEL_N LVCMOS18 8 NONE NA NA OFF NA NA NA 1.8
tmds_data_p[0] - 30/2 Y out IOR15[A] - LVCMOS33D 8 NONE NA NA NA NA OFF NA 3.3
tmds_data_p[1] - 32/2 Y out IOR11[A] GCLKT_3 LVCMOS33D 8 NONE NA NA NA NA OFF NA 3.3
tmds_data_p[2] - 35/2 Y out IOR2[A] RPLL_T_in LVCMOS33D 8 NONE NA NA NA NA OFF NA 3.3
tmds_data_n[0] - 22/3 N out IOB22[A] GCLKT_4 LVCMOS18 8 NONE NA NA OFF NA NA NA 1.8
tmds_data_n[1] - 23/3 N out IOB22[B] GCLKC_4 LVCMOS18 8 NONE NA NA OFF NA NA NA 1.8
tmds_data_n[2] - 20/3 N out IOB16[A] GCLKT_5 LVCMOS18 8 NONE NA NA OFF NA NA NA 1.8

All Package Pins:

Loc./Bank Signal Dir. Site CFG IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor Bank Vccio
3/0 - in IOT2[A] TDI LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
4/0 - out IOT2[B] TDO LVCMOS18 8 NONE NA NA OFF NA NA NA 1.8
6/0 - in IOT3[A] TMS LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
7/0 - in IOT3[B] TCK LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
8/0 tmds_clk_n out IOT4[B] JTAGSEL_N LVCMOS18 8 NONE NA NA OFF NA NA NA 1.8
9/0 - in IOT5[B] DONE LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
10/0 - in IOT7[A] MODE1 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
1/0 - in IOT10[A] MCLK/D4 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
2/0 - in IOT10[B] MCS_N/D5 LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
48/1 - in IOT11[A] MO/D6 LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
47/1 - in IOT11[B] MI/D7 LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
45/1 clk in IOT13[A] LPLL_T_in LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
46/1 - in IOT13[B] LPLL_C_in LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
43/1 - in IOT17[A] GCLKT_0 LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
44/1 - in IOT17[B] GCLKC_0 LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
41/1 - in IOT20[A] GCLKT_1 LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
42/1 - in IOT20[B] GCLKC_1 LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
39/1 - in IOT26[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
40/1 - in IOT26[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
13/3 - in IOB4[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
14/3 rst_n in IOB4[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
15/3 - in IOB5[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
p1-22/3 - in IOB5[B] - LVCMOS18 - UP - - - - - - -
16/3 - in IOB6[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
17/3 - in IOB6[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
p1-19/3 - in IOB7[A] - LVCMOS18 - UP - - - - - - -
p1-18/3 - in IOB7[B] - LVCMOS18 - UP - - - - - - -
18/3 - in IOB13[A] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
19/3 - in IOB13[B] - LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
p1-17/3 - in IOB14[A] - LVCMOS18 - UP - - - - - - -
p1-16/3 - in IOB14[B] - LVCMOS18 - UP - - - - - - -
p1-15/3 - in IOB15[A] - LVCMOS18 - UP - - - - - - -
p1-14/3 - in IOB15[B] - LVCMOS18 - UP - - - - - - -
20/3 tmds_data_n[2] out IOB16[A] GCLKT_5 LVCMOS18 8 NONE NA NA OFF NA NA NA 1.8
21/3 led out IOB16[B] GCLKC_5 LVCMOS18 8 NONE NA NA OFF NA NA NA 1.8
22/3 tmds_data_n[0] out IOB22[A] GCLKT_4 LVCMOS18 8 NONE NA NA OFF NA NA NA 1.8
23/3 tmds_data_n[1] out IOB22[B] GCLKC_4 LVCMOS18 8 NONE NA NA OFF NA NA NA 1.8
p1-13/3 - in IOB23[A] - LVCMOS18 - UP - - - - - - -
p1-10/3 - in IOB24[B] - LVCMOS18 - UP - - - - - - -
p1-9/3 - in IOB25[A] - LVCMOS18 - UP - - - - - - -
p1-8/3 - in IOB25[B] - LVCMOS18 - UP - - - - - - -
p1-7/3 - in IOB29[A] - LVCMOS18 - UP - - - - - - -
p1-6/3 - in IOB29[B] - LVCMOS18 - UP - - - - - - -
35/2 tmds_data_p[2](p) out IOR2[A] RPLL_T_in LVCMOS33D 8 NONE NA NA NA NA OFF NA 3.3
34/2 tmds_data_p[2](n) out IOR2[B] RPLL_C_in LVCMOS33D 8 NONE NA NA NA NA OFF NA 3.3
33/2 - in IOR9[B] GCLKC_2 LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
32/2 tmds_data_p[1](p) out IOR11[A] GCLKT_3 LVCMOS33D 8 NONE NA NA NA NA OFF NA 3.3
31/2 tmds_data_p[1](n) out IOR11[B] GCLKC_3 LVCMOS33D 8 NONE NA NA NA NA OFF NA 3.3
30/2 tmds_data_p[0](p) out IOR15[A] - LVCMOS33D 8 NONE NA NA NA NA OFF NA 3.3
29/2 tmds_data_p[0](n) out IOR15[B] - LVCMOS33D 8 NONE NA NA NA NA OFF NA 3.3
28/2 tmds_clk_p(p) out IOR17[A] - LVCMOS33D 8 NONE NA NA NA NA OFF NA 3.3
27/2 tmds_clk_p(n) out IOR17[B] - LVCMOS33D 8 NONE NA NA NA NA OFF NA 3.3